1/4 rev. c sturucture silicon monolithic integrated circuit type 4 channel switching regulator control system for dsc producut series BD9855MWV thysical dimensions package(plastic mold) fig.1 block diagram fig.2 pin description fig.3 features include step-down 2ch,cross converter 1ch,step down/inverting 1ch. short circuit protection (scp), under voltage lockout function (uvlo), include external synchronous rectification operation independent on/off function each channel uqfn044v6060 package 0.4mm pitch absolute maxi mum ratings ta = 2 5 (*1) without external heat sink, the power dissipation degrades by 4.2mw/ above 25 . (*2)power dissipation degrades by 8.0mw/ above 25 , when mounted on a pcb (70mm70mm1.6mm). operating conditions parameter symbol spec. unit condition min typ max input voltage power supply voltage vcc,pvcc 4 6 14 v reference output vreg,vrega terminal capacitor cvr* 0.47 1.0 2.2 f vref terminal capacitor cvref 0.047 0.1 2.2 f protect circuit scp terminal capacitor cscp 0.001 2.2 f oscillator oscillator frequency fosc 0.6 1.0 1.5 mhz osc timming resistor rt 47 82 120 k rtss terminal capacitor crtss 1000 10000 pf sync terminal input h vsynch 3.0 - vcc v sync terminal input l vsyncl -0.3 - 0.5 v sync terminal input duty dsync 40 50 60 % driver bst-lx voltage vbst 3.5 5.5 v bst-lx capacitor cbst 0.047 0.1 0.22 f lx31terminal input voltage vlx31 14 v ch3 output range vvout3 4.0 7.0 v pvcc1,2,4 terminal input voltage pvcc1,2,4 14 v ch1,2,3output current ioutch1,2,3 1 a )please connect capacitor at input/output terminal (vcc,pvcc,v ref,vreg etc.) to operate ic stabilize. status of this document the japanese language version of this document shall be the off icial specification. any translation of this document shall be for reference only. parameter symbol limits units power supply voltage vcc,pvcc 0.3 15 v input voltage bst1-lx1 bst2-lx2 0.3 7 v lx31 0.3 15 v vo3,lx32 0.3 8.4 v pg,sync, ctl1,2,3,4 0.3 15 v sel 0.3 7 v power dissipation pd 540(*1),1000(*2) mw operating temperature top r 25 +85 storage temperature ts t g 55 +150 junction temperature tjmax 150
2/4 rev. c electrical characteristics ta = 2 5 vcc=pvcc=6v, rt=82kohm, ctl1 4=3v with no designation the protective circuit start working when circuit is operated by 100% duty. so it is possible to use only for transition time shorter than charge time for scp. this product is not designed for normal operation with in a ra dioactive environment. ireg=1ma ireg=1ma vccmonitor,vregmonitor vcc cancel ,vreg cancel fb pin monitor vscp=0.1v rt=82k?sel=gnd rt=82k?sel=vrega vscp=0v ctl14=0v inv14, non4=0v ch13 non4=1v, inv4=fb4 vcc=4.88.4v iref=10a100a vref=0v vscp=0.1v vss=0.2v ilx=50ma ilx=-50ma iout3=50ma iout3=-50ma ilx=-50ma vo3=6.0v, ilx=50ma ilx=-50ma iout4=50ma,inv4=1.1v iout4=-50ma,inv4=0.9v pg=1v pg=15v ctl14=0v inv=2.5v,non=1v all ch on test circuit parameter symbol standard value units conditions min typ max regulator output voltage for boost terminal vreg 4.8 5 5.2 v internal regulator 2.6 v under voltage lock function regulator output voltage for inside standard vrega 2.4 2.5 threshold voltage,2 vstd1,2 3.4 3.6 3.8 v hysterisis voltage width vhys1,2 0.1 0.2 v short circuit protection timer start threshold voltage vtc 2.1 2.2 2.3 v scp out source voltage iscp1 2.5 5 7.5 a scp threshold voltage vtsc 0.45 0.5 0.55 v 100 mv oscillator stand by voltage vssc 10 frequency ch13 fosc123 0.8 1 1.2 mhz frequency ch4 fosc4 0.4 0.5 0.6 mhz max duty 1,2(step down) dmax1,2 - - 100 % max duty ch3 lx31 dmax31 - - 100 % max duty ch3 lx32 dmax32 78 84 90 % max duty 4 dmax4 86 92 96 % rtss pin standby voltage rtssf - 1 20 mv rtss pin smk current irtssi -7 -5 -3 a 7 a error amp rtss pin source current irtsso 3 5 input bias current iinv - 30 100 na inv threshold voltage 1 vinv1 0.79 0.8 0.81 v 5 mv reference voltage vref non_invoffset voltage voff - - vrefoutput voltage voref 0.99 1 1.01 v line regulation dvli - 1 7.5 mv load regulation dvlo - 1 7.5 mv output current when shorted ios 2 10 - ma soft start s s1,2,3,4source current iss 12 3 a 1000 output driver ss discharge resistance rdisss -5 0 0 ch1,2 highside sw on resistance ron12p -2 0 03 5 0m ch1,2 highside sw on resistance ron12n -1 5 03 0 0m ch3 driver output voltage h vout3h pvcc-1.0 pvcc -0.5 - v ch3 driver output voltage l vout3l -0 . 5 1v ch3 lx31pin lowside sw on resistance ron31n -2 5 04 0 0m ch3 lx32pin highside sw on resistance ron32p -2 0 03 5 0m ch3 lx32pin lowside sw on resistance ron32n -1 5 03 0 0m ch4 driver output voltage h vout4h pvcc-1.0 pvcc -0.5 - v 1v pg output pin ch4 driver output voltage l vout4l -0 . 5 pg pin on resistance ronpg -0 . 5 1k pg pin leak current ilkpg -0 1u a vctll -0.3 - 0.8 circuit currentvcc,pvcc pin input current icc - 4 circuit currentapplication io=none iccapl 8 ma control terminal ctl terminal voltage(on), vctlh 2 - vcc v v ctl,sel pull down resistance rctl,rsel 250 400 700 k ctl terminal voltage (off), circuit current stand-by current istb - 05 a - 25 35 ma vselh vsell sel terminal voltage (? frequency) sel terminal voltage (same frequency) -0.3 2 0.8 7 - - - v v sel=vrega
3/4 rev. c package plastic mold (unitmm) fig.1 block diagram pin description + - + erroramp1 inv1 fb1 + - + erroramp2 inv2 fb2 + - + erroramp3 inv3 fb3 erroramp4 pwmcomp4 inv4 fb4 non4 + - vref + - scp timer protection tsd uvlo osc ch_ctl vreg out4 pgnd4 vcc ctl1 ctl2 ctl3 ctl4 rt vreg gnd vref sync ch2 step down (current mode) ch1 step down (current mode) lx1 pgnd12 pvcc1 lx2 pvcc2 ch3 cross converter out3 lx31 pgnd3 lx32 vo3 pvcc4 bst2 - - - - + pvcc4 osc sync ss1 ss2 ss3 scp sel latch ss4 bst1 ss monitor bst1 bst2 bst2 bst1 latch latch vrega vrega pg rtss fig.2 fig.3 bd9855 lot no.
4/4 rev. c operation notes 1.) absolute maximum ratings use of the ic in excess of ab solute maximum ratings such as the applied voltage or operating temperature range may result in ic deterioration or damage. assumptions should not be made regarding the state of the ic (short mode or open mode) when such damage is suffered. a physical safety measure such as a fuse should be implemented when use of the ic in a special mode where the absolute maximum ratings may be exceeded is anti cipated. 2.) gnd potential ensure a minimum gnd pin potential in all operating conditions. in addition, ensure that no pins other than the gnd pin carry a voltage lower than or equal to the gnd pin(except inv4 terminal), including during actual transient phenomena. 3.) thermal design use a thermal design that allows for a sufficient margin in li ght of the power dissipation (pd) in actual operating conditions. 4.) inter-pin shorts and mounting errors use caution when orienting and positioning the ic for mounting on printed circuit boards. improper mounting may result in damag e to the ic. shorts between output pins or between output pins and the power supply and gnd pi n caused by the presence of a foreign object may result in da mage to the ic. 5.) operation in a strong electromagnetic field use caution when using the ic in the presen ce of a strong electromagnetic field as doing so may cause the ic to malfunction. 6.) common impedance power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much a s possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance). 7.) voltage of ctl pin the threshold voltages of ctl pin are 0.8v and 2.0v. stb st ate is set below 0.8v while action state is set beyond 2.0v. the region between 0.8v and 2.0v is not recommended and may cause improper operation. the rise and fall time must be under 10msec. in case to put capacitor to stb pin, it is recommended to use under 0.01 f. 8.) thermal shutdown circuit (tsd circuit) this ic incorporates a built-in thermal shutdown circuit (tsd circuit). the tsd circuit is designed only to shut the ic off to prevent runaway thermal operation. do not continue to use the ic after operating this circuit or use the ic in an environment where the operation of the thermal s hutdown circuit is assumed. 9.) ic pin input this monolithic ic contains p+ isolat ion and pcb layers between adjacent element s in order to keep them isolated. p/n junctions are formed at the intersection of these p layers wi th the n layers of other elements to create a variety of paras itic elements. for example, when a resistor and transistor are connected to pins as shown in following chart, ? the p/n junction functions as a parasitic diode when gnd > (pin a) for the resistor or gnd > (pin b) for the transistor (npn). ? similarly, when gnd > (pin b) for the transistor (npn), the parasitic diode described above combines with the n layer of other adjacent elements to operate as a parasitic npn transistor. the formation of parasitic elements as a re sult of the relationships of the potentials of different pins is an inevitable resul t of the ic's architecture. the operation of parasitic elements can cause interference with ci rcuit operation as well as ic malfunction and damage. for these r easons, it is necessary to use caution so that the ic is not used in a way that will trigger the operation of parasi tic elements, such as by the application o f voltages lower than the gnd (pcb) voltage to input and output pins. fig.4 simplified structure of a bipolar ic pin ? gnd parasitic diode pin b parasitic elementals transistor (npn) gnd p substrate n p n n p p b n e c gnd pin a parasitic elementals p substrate n p n n p p resistance
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